Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed operations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
One approach to achieving the objectives of greater integration and smaller semiconductor devices is to focus on 2.5-D packaging technologies, i.e., electrical interconnection between adjacent semiconductor die within a device, and 3-D packaging technologies, i.e., electrical interconnection between vertically stacked semiconductor die or package-on-package (PoP) semiconductor devices.
In a fan-out embedded wafer level ball grid array (Fo-eWLB), electrical interconnect between adjacent semiconductor die, and between the semiconductor die and external devices is provided through a build-up interconnect structure. The build-up interconnect structure is formed over the semiconductor die and an encapsulant that surrounds the semiconductor die. The build-up interconnect structure typically includes multiple redistribution layers (RDL). When forming a build-up interconnect structure with fine or narrow pitch RDL, for example RDL having a pitch of 5 microns (μm), the encapsulated semiconductor die are bonded to a temporary carrier to prevent warpage during formation of the build-up interconnect structure. After the build-up interconnect structure is formed, a plurality of interconnect structures, for example conductive bumps, is formed over the build-up interconnect structure and then the temporary carrier is removed. Bonding and debonding the temporary carrier to the encapsulated semiconductor die adds steps to the manufacturing process, increases manufacturing time and cost, and reduces throughput. In addition, forming an Fo-eWLB having a build-up interconnect structure with ultra-fine pitch RDL, for example 2 μm or less, is difficult and involves complex, highly controlled, expensive, and time-consuming manufacturing steps.
The electrical interconnection between adjacent semiconductor die within a device and between the semiconductor die and external devices can also be accomplished by embedding a through silicon vias (TSV) interposer within the semiconductor package. In a 2.5D TSV package, RDL are formed over and conductive TSV are formed through an interposer to provide electrical interconnect. The conductive TSV and RDL route signals between semiconductor die disposed over the interposer and between the semiconductor die and external devices. The RDL formed on a TSV interposer are scalable to a submicron dimension, i.e., in a nanometer range; however, forming a TSV interposer package involves complex, expensive, and time-consuming manufacturing steps. In addition, the vertical interconnects of a TSV interposer consume space and increase the overall height of the package. Accordingly, TSV interposer packages cannot meet the X, Y, and Z, i.e., length, width, and height, requirements of smaller semiconductor devices.